As well known in the art, a silicon oxide film (SiO2) has been mainly used as a material of a gate insulating film in MOSFET and a polysilicon film has been used as a material of the gate. As the integration level of the semiconductor devices becomes higher, however, it is required that the line width of the gate and the thickness of the gate insulating film be reduced. In the case where a silicon oxide film is used as the material of the gate insulating film, if the thickness of the gate insulating film is too thin, the insulating characteristic is not stable since the leakage current due to a direct tunneling through the gate insulating film becomes greater.
For example, when a silicon oxide film is used as the gate insulating film of DRAM and logic devices, currently manufactured in mass production, is applied to a 70 nm thickness device, it is expected that its thickness will be 30 Å through 35 Å in DRAM and be 13 Å through 15 Å in logic devices. As the capacitor component, increased by a polysilicon gate depletion effect (PDE), is increased to be 3 Å through 8 Å, however, it is difficult to reduce the electrical thickness (Teff) occupied by a gate oxide film having a thickness in the range of 15 Å through 30 Å.
Therefore, as one method to overcome the above problem, recently there has been an effort to use a high dielectric constant material, having a relatively higher dielectric constant than a silicon oxide film, as the material of the gate insulating film. Also, in order to minimize the polysilicon gate depletion effect, there has been an effort to use a metal gate instead of the polysilicon gate.
In case of the metal gate, a TiN or a WN film, as a barrier metal film, is intervened between the metal film for the gate and the gate insulating film, and a hard mask film, used as an etch mask, is positioned on the metal film for the gate.
However, in the case of forming a metal gate on a silicon oxide gate insulating film according to a conventional technology, there is a problem that a characteristic of the gate insulating film is degraded as follows.
Deposition of a metal film for the gate is commonly performed by sputtering or chemical vapor deposition (CVD). However, by directly depositing the metal film for the gate by sputtering or CVD on a silicon gate insulating film, the interface characteristic and the insulating characteristic of the gate insulating film can be degraded.
FIGS. 1A and 1B are graphs illustrating capacitance (C)—voltage (V) curves of a MOS capacitor formed by sequentially directly depositing a TiN or a WN film as a barrier film and a tungsten (W) film, as a metal film gate, on a gate insulating film made of silicon oxide by means of sputtering according to a conventional technology.
As shown, in the embodiment that includes the steps of sequentially depositing the barrier metal film (TiN or WN) and the tungsten film gate on the silicon oxide gate insulating film, high levels of oxide defect charges are formed due to an excessive interface trap density of about 1E12/eV-cm2 and oxide trap charges of about 1E12/cm2 by means of a hump and a hysteresis, respectively, without significant regard to the deposited barrier metal film materials (TiN or WN) and sputtering methods (IMP, collimated, conventional) of the capacitance—voltage characteristic, with a subsequent annealing process not performed. Due to this, there is resulting damage to the gate insulating properties itself and severe damage in the interface with the substrate.
Meanwhile, the damage can be recovered to some degree through a high temperature annealing process of, for example, 800° C., but a complete recovery of the damaged gate insulating film cannot be achieved. Further, the high temperature annealing process is disadvantageous and costly and the electrical thickness (Teff) of the gate insulating film must be increased in order to recover some of the lost properties.
FIGS. 2A through 2C are graphs illustrating capacitance (C)—voltage (V) curves in the TiN metal gate, deposited in a thermal deposition method, of TiCl4+NH3 at 650° C.
As shown, the MOS transistor characteristic after deposition is relatively better than that deposited by a sputtering method. However, degradation of the gate oxide integrity (GOI) characteristic is caused due to an increase of the electrical thickness (Teff) and the oxide trap charges in the gate insulating film after a subsequent annealing process, that is, increased hysteresis. Particularly, severe degradation of the GOI characteristic can be caused when the MOS capacitors/transistor is manufactured.